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NCP1219 PWM Controller with Adjustable Skip Level and External Latch Input
The NCP1219 represents a new, pin to pin compatible, generation of the successful 7-pin current mode NCP12XX product series. The controller allows for excellent standby power consumption by use of its adjustable skip mode and integrated high voltage startup FET. Internal frequency jittering, ramp compensation, timer-based fault detection and a latch input make this controller an excellent candidate for converters where ruggedness and component cost are the key constraints. The Dynamic Self Supply (DSS) drastically simplifies the transformer design in avoiding the use of an auxiliary winding to supply the NCP1219. This feature is particularly useful in applications where the output voltage varies during operation (e.g. battery chargers). Due to its high voltage technology, the IC can be directly connected to the high voltage dc rail.
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SOIC-7 D SUFFIX CASE 751U
MARKING DIAGRAM
8 1219XZ ALYW G
1
* Fixed-Frequency Current-Mode Operation with Ramp * * * * * * * * * * * * *
Compensation (65 kHz and 100 kHz Options) Dynamic Self Supply Eliminates the Need for an Auxiliary Winding Timer-Based Fault Protection for Improved Overload Detection Cycle Skip Reduces Input Power in Standby Mode Latch and Auto-Recovery Overload Protection Options Internal High Voltage Startup Circuit Accurate Current Limit Detector (5%) Adjustable Skip Level Latch Input for Easy Implementation of Overvoltage and Overtemperature Protection Frequency Modulation for Softened EMI Signature 500 mA/800 mA Peak Source/Sink Current Drive Capability Pin to Pin Compatible with the Existing NCP12XX Series These are Pb-Free Devices These are Halide-Free Devices
1219 = Specific Device Code X = Overcurrent = (A = latch, B = auto-retry) Z = Frequency = (6 = 65 kHz, 1 = 100 kHz) A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package
PIN CONNECTIONS
Skip/latch FB CS GND (Top View) VCC Drv 1 HV
Typical Applications
* AC-DC Adapters for Notebooks, LCD Monitors * Offline Battery Chargers * Consumer Electronic Appliances STB, DVD, DVDR
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
May, 2009 - Rev. 1
1
Publication Order Number: NCP1219/D
NCP1219
+
AC Input
EMI Filter
Output Voltage
- latch input*
* Optional
Skip/latch HV FB VCC CS GND DRV NCP1219 Rramp*
Figure 1. Typical Application Circuit
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2V Skip/latch Rupper 42.0k* Rlower 51.3k* VSkip VSkip(max) VFB(open) FB VFB 16.7k* VSkip/latch Skip Comparator + Soft-Start/PWM Clamp
Vlatch + 50 ms* filter
Latched overload (Option A) latch-off, reset when VCC < VCC(reset) R S (Option A) Q
Istart when VCC > Vinhibit Iinhibit when VCC < Vinhibit R S Q + VCC(on) TSD + Normal = VCC(min) Fault = VCC(hiccup)
- +
HV
Rskip
VFB / 3
VILIM tSSTART clamp detect time
soft- start set
75 ms* filter
VCC(reset) UVLO + Fault Management Double Hiccup Counter VCC
tOVLD timer reset PWM +
Iramp(peak) 0
VDD
CS Rramp CS RCS VCS
Iramp
LEB
Maximum Duty Ratio detect Oscillator R S
disable internal bias Q
VCC DRV
GND
7.5%* Jittering
* Typical values are shown
Figure 2. Functional Block Diagram
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Table 1. PIN FUNCTION DESCRIPTION
Pin 1 Name Skip/latch Description This pin provides a latch input to permanently disable the device under a fault condition. It also allows the user to adjust the skip threshold. A resistor between this pin and GND provides noise immunity to the latch input and sets the skip threshold. The voltage on this pin is determined by the combination of the internal voltage divider and the external resistor to ground. The default skip threshold is 1.1 V (typical) if no external resistor is used. An internal clamp prevents the skip level from increasing above 1.3 V if the Skip/latch pin is pulled high to latch the controller. The voltage on this pin is proportional to the output load on the converter. An internal resistor divider sets the voltage on this pin above the regulation threshold (3 V) and an external optocoupler pulls the pin low to achieve regulation. While the FB voltage is above its regulation threshold, the overload timer is enabled. If the overload timer expires, the controller enters a double hiccup mode (option B) or is latched (option A) depending on the version of the device. The converter enters skip mode if the FB voltage is below the skip threshold. A voltage ramp proportional to the primary current is applied to this pin. The maximum current is reached once the ramp voltage reaches 1 V (typical). A 100 mA (typical) current source provides ramp compensation. The amount of ramp compensation is adjusted with a series resistor between the CS pin and the current sense resistor. Analog ground. Main output of the PWM Controller. DRV has a source resistance of 12.6 W (typical) and a sink resistance of 6.7 W (typical). Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from the HV pin to this pin. Once the VCC voltage reaches VCC(on) (12.7 V typical), the current source turns off and the DRV is enabled. The current source turns on once VCC falls to VCC(min) (9.9 V typical). This mode of operation is known as dynamic self supply (DSS). If the bias current consumption exceeds the startup current, and VCC drops 0.5 V (typical) below VCC(min) the converter turns off and enters a double hiccup mode. If the VCC voltage is below 0.67 V (typical) the startup current is reduced to 200 mA (typical), reducing power dissipation. This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A controlled current source supplies current from this pin to the VCC capacitor, eliminating the need for an external startup resistor. The charge current is 12.8 mA (typical).
2
FB
3
CS
4 5 6
GND DRV VCC
8
HV
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Table 2. MAXIMUM RATINGS (Notes 1 - 4)
Rating HV Voltage HV Current Supply Voltage Supply Current Skip/latch Voltage Skip/latch Current FB Voltage FB Current CS Voltage CS Current DRV Voltage DRV Current Operating Junction Temperature Storage Temperature Range Power Dissipation (TA = 25C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751U (SOIC-7) (Note 4) Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751U (SOIC-7) Junction to Air, Low conductivity PCB (Note 3) Junction to Lead, Low conductivity PCB (Note 3) Junction to Air, High conductivity PCB (Note 4) Junction to Lead, High conductivity PCB (Note 4) Symbol VHV IHV VCC ICC VSkip/latch ISkip/latch VFB IFB VCS ICS VDRV IDRV TJ Tstg PD Value -0.3 to 500 100 -0.3 to 20 100 -0.3 to 9.5 100 -0.3 to 5.0 100 -0.3 to 5.0 100 -0.3 to 20 -500 to 800 -40 to 150 -60 to 150 0.92 Unit V mA V mA V mA V mA V mA V mA C C W C/W RJA RJL RJA RJL 177 75 136 69
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pins 1- 6: Human Body Model 3000 V per JEDEC JESD22-A114-F . Pins 1- 6: Machine Model Method 300 V per JEDEC JESD22-A115-A. Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V. 2. This device contains Latch-Up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow. 4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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Table 3. ELECTRICAL CHARACTERISTICS (VHV = 60 V, VCC = 11.3 V, VFB = 2 V, VSkip/latch = 0 V, VCS = 0 V, VDRV = open, CCC = 0.1 mF, for typical values TJ = 25C, for min/max values, TJ is -40C to 125C, unless otherwise noted)
Characteristics STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Operating Voltage Undervoltage Lockout Double Hiccup Threshold Logic Reset Voltage UVLO Filter Delay Inhibit Threshold Voltage Inhibit Bias Current Minimum Startup Voltage Startup Current Startup Circuit Reverse Current Off-State Leakage Current Breakdown Voltage (Note 5) Supply Current Device Disabled/Fault Device Enabled/No Switching Device Switching (65 kHz) Device Switching (100 kHz) CURRENT SENSE Current Sense Voltage Threshold Leading Edge Blanking Duration Propagation Delay Ramp Compensation Peak Current Ramp Compensation Valley Current FEEDBACK INPUT Open Feedback Voltage Internal Pull-up Resistance Feedback Pull-up Current Feedback to Current Set Point Ratio SOFT-START Soft-Start Period OSCILLATOR Oscillator Frequency 65 kHz Option fOSC TJ = 25_C TJ = -40_C to 85_C TJ = -40_C to 125_C TJ = 25_C TJ = -40_C to 85_C TJ = -40_C to 125_C 61.75 58 55 95 89 85 - - D 75 65 - - 100 - - 7.5 6.0 80 68.25 71 71 105 107 107 - - 85 % ms % kHz Measured at 0.9 VILIM tSSTART - 4.8 - ms VFB = 0 V VFB(open) RFB IFB Iratio 3.2 - 141 - 3.6 16.7 280 3.0 3.9 - 392 - V kW mA VCS > VILIM to 50% DRV turns off, CDRV = 1000 pF Apply voltage step on CS pin VILIM tLEB tdelay Iramp(peak) Iramp(valley) 0.95 100 - - - 1.0 184 59 100 0 1.05 330 150 - - V ns ns mA mA Iinhibit = 500 mA VCC = 0 V Istart = 0.5 mA, VCC = VCC(on) - 0.5 V VCC = VCC (on) - 0.5 V VHV = 0 V, VCC = 14 V VHV = 500 V, VCC = 14 V IHV = 50 mA VSkip/latch = 5.2 V, VFB = open VSkip/latch = open, VFB = 0 V VSkip/latch = open, CDRV = 1000 pF VSkip/latch = open, CDRV = 1000 pF V VCC Increasing VCC Decreasing VCC Decreasing VCC Decreasing VCC Decreasing VCC(on) VCC(MIN) UVLO VCC(hiccup) VCC(reset) tUVLO(delay) Vinhibit Iinhibit Vstart(min) Istart IHV(reverse) IHV(off) VBR(DS) ICC1 ICC2 ICC3A ICC3B 11.2 9.0 8.4 4.9 - - 0.35 100 - 5.5 - - 500 - - - - 12.7 9.9 9.4 5.7 4.0 50 0.67 200 20 12.8 - 12 - 0.6 1.4 2.2 2.4 13.8 10.8 10.6 6.3 - - 0.90 350 28 18.5 100 50 - 0.8 2.1 2.7 3.2 ms V mA V mA mA mA V mA Conditions Symbol Min Typ Max Unit
100 kHz Option
Frequency Modulation in Percentage of fOSC Frequency Modulation Period Maximum Duty Ratio 5. Guaranteed by the IHV(off) test. 6. Guaranteed by design only.
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Table 3. ELECTRICAL CHARACTERISTICS (VHV = 60 V, VCC = 11.3 V, VFB = 2 V, VSkip/latch = 0 V, VCS = 0 V, VDRV = open, CCC = 0.1 mF, for typical values TJ = 25C, for min/max values, TJ is -40C to 125C, unless otherwise noted)
Characteristics GATE DRIVE Drive Resistance DRV Sink DRV Source Rise Time (10% to 90%) Fall Time (90% to 10%) LATCH INPUT Latch Voltage Threshold Latch Filter Delay CYCLE SKIP Default Skip Threshold Skip Clamp Voltage Skip Comparator Hysteresis Skip Clamp Comparator Hysteresis Skip Current FAULTS PROTECTION Thermal Shutdown (Note 6) Thermal Shutdown Hysteresis Thermal Shutdown Delay Overload Timer 5. Guaranteed by the IHV(off) test. 6. Guaranteed by design only. Apply voltage step on FB pin Temperature Increasing Temperature Decreasing TSHDN TSHDN(HYS) TSHDN(delay) tOVLD - - - - 155 40 75 118 - - - - C C ms ms VFB increasing, VSkip/latch = Open VFB increasing, VSkip/latch = 2.0 V VFB decreasing, VSkip/latch = 0.5 V VFB decreasing, VSkip/latch = 2.0 V VSkip/latch = 0 V Vskip Vskip(MAX) Vskip(HYS1) Vskip(HYS2) Iskip 0.9 1.1 - - 30 1.1 1.3 75 75 47 1.3 1.5 - - 56 V V mV mV mA VSkip/latch = 5.2 V, apply voltage step on Skip/latch pin Vlatch tlatch(delay) 3.4 - 3.9 50 4.6 - V ms W VFB = 0 V, VDRV = 1 V VDRV = VCC - 1 V CDRV = 1000 pF (10% to 90%) CDRV = 1000 pF (90% to 10%) RSNK RSRC tr tf 2.0 6.0 - - 6.7 12.6 30 20 13 25 - - ns ns Conditions Symbol Min Typ Max Unit
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TYPICAL CHARACTERISTICS
15 13 12 11 9 8 7 6 5 -50 10 VCC(on) VCC(MIN) UVLO Vinhibit, INHIBIT THRESHOLD VOLTAGE (V) 14 VCC, SUPPLY VOLTAGE THRESHOLDS (V) 1.40 1.26 1.12 0.98 0.84 0.70 0.56 0.42 0.28 0.14 0 -50 Iinhibit = 500 mA
VCC(reset) -25 0 25 50 75 100 125
150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 3. Supply Voltage Thresholds vs. Junction Temperature
300 Istart, STARTUP CURRENT (mA) Iinhibit, INHIBIT CURRENT (mA) 280 260 240 220 200 180 160 140 120 100 -50 -25 0 25 50 75 100 125 150 VCC = 0 V 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -50
Figure 4. Inhibit Threshold Voltage vs. Junction Temperature
VHV = 60 V VCC = VCC(on) - 0.5 V
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. Inhibit Current vs. Junction Temperature
16 Istart, STARTUP CURRENT (mA) 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 30 VHV = 60 V Istart(off), STARTUP CIRCUIT LEAKAGE CURRENT (mA) 27 24 21 18 15 12 9 6 3 0 -50
Figure 6. Startup Current vs. Junction Temperature
VHV = 60 V VCC = 14 V
-25
0
25
50
75
100
125
150
VCC, SUPPLY VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (C)
Figure 7. Startup Current vs. Supply Voltage
Figure 8. Startup Circuit Leakage Current vs. Junction Temperature
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TYPICAL CHARACTERISTICS
50 ICC, SUPPLY CURRENT (mA) 45 Istart(off), STARTUP CIRCUIT LEAKAGE CURRENT (mA) 40 35 30 25 TJ = -40C 15 5 0 TJ = 125C 0 75 150 225 300 375 450 525 20 10 VCC = 14 V 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0.0 -50 ICC1 -25 0 25 50 75 100 125 150 ICC2 ICC3 (fOSC ~ 65 kHz) ICC3 (fOSC ~ 100 kHz)
VHV, HV VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Startup Circuit Leakage Current vs. HV Voltage
ICC3, OPERATING SUPPLY CURRENT (mA) 4.0 VILIM, CURRENT SENSE VOLTAGE THRESHOLD (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 9 10 11 12 13 14 15 16 17 18 19 20 21 TJ = 25C 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 -50
Figure 10. Supply Current vs. Junction Temperature
fOSC = 100 kHz fOSC = 65 kHz
-25
0
25
50
75
100
125
150
VCC, SUPPLY VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (C)
Figure 11. Operating Supply Current vs. Supply Voltage
tLEB, LEADING EDGE BLANKING TIME (ns) 300 280 260 240 220 200 180 160 140 120 100 -50 -25 0 25 50 75 100 125 150 tdelay, CURRENT SENSE PROPAGATION DELAY (ns) 125 115 105 95 85 75 65 55 45 35 25 -50
Figure 12. Current Sense Voltage Threshold vs. Junction Temperature
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. Leading Edge Blanking Time vs. Junction Temperature
Figure 14. Current Sense Propagation Delay vs. Junction Temperature
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TYPICAL CHARACTERISTICS
fOSC, OSCILLATOR FREQUENCY (kHz)
120
100 kHz Option D, MAXIMUM DUTY RATIO (%)
85 84 83 82 81 80 79 78 77 76 75 -50 -25 0 25 50 75 100 125 150
110 100 90 80 70 60 50 40 -50 -25 0 25 50 75 100 125 150
65 kHz Option
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 15. Oscillator Frequency vs. Junction Temperature
RSNK/RSRC, DRIVE SINK/SOURCE RESISTANCE (W) 18 16 14 VCC = 11.3 V Vlatch, LATCH VOLTAGE THRESHOLD (V) 20 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 -50
Figure 16. Maximum Duty Ratio vs. Junction Temperature
12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 Source, VDRV = VCC - 1 V Sink, VDRV = 1 V
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 17. Drive Sink and Source Resistances vs. Junction Temperature
Vskip, DEFAULT SKIP THRESHOLD (V) 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 VSkip/latch = open Vskip(MAX), SKIP CLAMP VOLTAGE (V) 1.30 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 -50
Figure 18. Latch Voltage Threshold vs. Junction Temperature
VSkip/latch = 2 V
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 19. Default Skip Threshold vs. Junction Temperature
Figure 20. Skip Clamp Voltage vs. Junction Temperature
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TYPICAL CHARACTERISTICS
Vskip2, ADJUSTABLE SKIP THRESHOLD (V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 -50 -25 0 25 50 75 100 125 150 Rskip = 48.7 kW Vskip, SKIP THRESHOLD (V) 1.0 0.8 0.6 0.4 0.2 0 1.2
1
10
100
1000
10000
TJ, JUNCTION TEMPERATURE (C)
RSkip, EXTERNAL SKIP RESISTOR (kW)
Figure 21. Adjustable Skip Threshold vs. Junction Temperature
tOVLD, OVERLOAD TIMER PERIOD (ms) 10 tSSTART, SOFT-START PERIOD (ms) 9 8 7 6 5 4 3 2 1 0 -50 140 135 130 125 120 115 110 105 100 95 90 -50
Figure 22. Skip Threshold vs. Skip Resistor
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 23. Soft-Start Period vs. Junction Temperature
Figure 24. Overload Timer Period vs. Junction Temperature
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DETAILED OPERATING DESCRIPTION The NCP1219 is part of a product family of current mode controllers designed for ac-dc applications requiring low standby power. The controller operates in skip or burst mode at light load. Its high integration reduces component count resulting in a more compact and lower cost power supply. This device family has 2 options, A and B. Option A latches where as option B auto restarts after an overload fault. The internal high voltage startup circuit with dynamic self supply (DSS) allows the controller to operate without an auxiliary supply, simplifying the transformer design. This feature is particularly useful in applications where the output voltage varies during operation (e.g. printer adapters). Other features found in the NCP1219 are frequency jittering, adjustable ramp compensation, timer based fault detection and a dedicated latch input.
High Voltage Startup Circuit
The NCP1219 internal high voltage startup circuit eliminates the need for external startup components and provides a faster startup time compared to an external startup resistor. The startup circuit consists of a constant current source that supplies current from the HV pin to the supply capacitor on the VCC pin (CCC). The HV pin is rated at 500 V allowing direct connection to the bulk capacitor. The start-up current (Istart) is typically 12.8 mA. The startup current source is disabled once the VCC voltage reaches VCC(on), typically 12.7 V. The controller is then biased by the VCC capacitor. The current source is enabled once the VCC voltage decays to its minimum operating threshold (VCC(MIN)) typically 9.9 V. If the
VCC(on)
supply current consumption exceeds the startup current, VCC will decay below VCC(MIN). The NCP1219 has an undervoltage lockout (UVLO) to prevent operation at low VCC levels. The UVLO threshold is typically 9.4 V. The DRV signal is immediately disabled upon reaching UVLO. It is re-enabled if VCC increases above UVLO before the 50 ms (typical) timer expires. Otherwise, the controller enters double hiccup mode. The controller enters a double hiccup mode if an overload (option B), thermal shutdown, UVLO or latch fault is detected. A double hiccup fault disables the DRV signal, sets the controller in a low current mode and allows VCC to discharge to VCC(hiccup), typically 5.7 V. This cycle is repeated twice to minimize power dissipation in external components during a fault event. Figures 25 and 26 show double hiccup mode operation with a fault occurring while the startup circuit is disabled and enabled, respectively. A soft-start sequence is initiated the second time VCC reaches VCC(on). If the fault is present or the controller is latched upon reaching VCC(on), the controller stays in hiccup mode. During this mode, VCC never drops below 4 V, the controller logic reset level. This prevents latched faults from being cleared unless power to the controller is completely removed (i.e. unplugging the supply from the AC line). There are two options available in the NCP1219, options A and B. Option A latches off after the overload timer expires if an overload fault is detected. In this case, VCC cycles between VCC(on) and VCC(hiccup) without enabling the DRV signal until the power to the controller is reset. On the other hand, option B has auto-retry circuitry allowing the DRV signal to restart after a double hiccup sequence triggered by an overload condition.
VCC(MIN) UVLO VCC(hiccup) VCC(reset) Fault1 Fault
DRV
ON
OFF
ON
Figure 25. VCC Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Disabled.
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VCC(on)
VCC(MIN) UVLO VCC(hiccup) VCC(reset) Fault2 Fault
DRV
ON
OFF
ON
Figure 26. VCC Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Enabled
An internal supervisory circuit monitors the VCC voltage to prevent the controller from dissipating excessive power if the VCC pin is accidentally grounded. A lower level current source (Iinhibit) charges CCC from 0 V to Vinhibit, typically 0.67 V. Once VCC exceeds Vinhibit, the startup current source is enabled. This behavior is illustrated in Figure 27. This slightly increases the total time to charge VCC, but it is generally not noticeable.
Startup Current
In comparison, the power dissipation when the startup circuit is disabled and VCC is being supplied by the auxiliary winding is a function of the VCC voltage. This is shown in Equation 2.
PAUX + I CC3 @ V CC
(eq. 2)
It is recommended that an external filter capacitor be placed as close as possible to the VCC pin to improve the noise immunity.
Soft-Start Operation
Istart
Iinhibit Vinhibit VCC(MIN) VCC(on)
VCC
The start-up circuit is rated at a maximum voltage of 500 V. If the device operates in the DSS mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. If dissipation on the controller is excessive, a resistor can be placed in series with the HV pin. This will reduce power dissipation on the controller and transfer it to the series resistor. Standby mode losses and normal mode power dissipation can be reduced by biasing the controller with an auxiliary winding. The auxiliary winding needs to maintain VCC above VCC(MIN) once the startup circuit is disabled. The power dissipation of the controller when operated in DSS mode, PDSS, can be calculated using equation 1, where ICC3 is the operating current of the NCP1219 during switching and VHV is the voltage at the HV pin. The HV pin is most often connected to the bulk capacitor.
PDSS + I CC3 @ (V HV * V CC)
(eq. 1)
Figure 27. Startup Current at Various VCC Levels
Figures 28 and 29 show how the soft-start feature is included in the pulse-width modulation (PWM) comparator. When the NCP1219 starts up, a soft-start voltage VSSTART begins at 0 V. VSSTART increases gradually from 0 V to 1.0 V in 4.8 ms and stays at 1.0 V afterward. VSSTART is compared with the divided by 3 feedback pin voltage (VFB/3). The lesser of VSSTART and (VFB/3) becomes the modulation voltage, VPWM, in the PWM duty ratio generation. Initially, (VFB/3) is above 1.0 V because the FB pin is brought to VFB(open), typically 3.6 V, by the internal pullup resistor. As a result, VPWM is limited by the soft-start function and slowly ramps up the duty ratio (and therefore the primary current) for the initial 4.8 ms. This provides a greatly reduced stress on the power devices during startup.
VSSTART VFB/3 0 - ) 1
VPWM
Figure 28. VPWM is the lesser of VSSTART and (VFB/3)
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Soft-start voltage, VSSTART Iramp(peak) 1V Iramp Vbulk
tSSTART Feedback pin voltage divided by 3, VFB/3 1V
R S 80% max duty Q Clock
VPWM (1 V max. signal)
Figure 30. Current-Mode Implementation
time must be less than tOVLD to prevent fault condition time
Pulse Width Modulation voltage, VPWM 1V
Figure 31 shows the timing diagram for the current-mode pulse width modulation operation. An internal clock sets the output RS latch, pulling the DRV pin high. The latch is then reset when the voltage on the CS pin intersects the modulation voltage, VPWM. This generates the duty ratio of the DRV pulse. The maximum duty ratio is internally limited to 80% (typical) by the output RS latch.
PWM Output
time tSSTART Drain Current, ID
time tSSTART
Figure 29. Soft-Start (Time = 0 at VCC = VCC(on)) Current-Mode Pulse Width Modulation
clock
The NCP1219 is a current-mode, fixed frequency pulse width modulation controller with ramp compensation. The PWM block of the NCP1219 is shown in Figure 30. The DRV signal is enabled by a clock pulse. At this time, current begins to flow in the power MOSFET and the sense resistor. A corresponding voltage is generated on the CS pin of the device, ranging from very low to as high as the maximum modulation voltage, VPWM (maximum of 1 V). This sets the primary current on a cycle-by-cycle basis. Equation 3 gives the maximum drain current, ID(MAX), where RCS is the current sense resistor value and VILIM is the current sense voltage threshold.
ID(MAX) + V ILIM R CS
(eq. 3)
Figure 31. Current-Mode Timing Diagram
The VPWM voltage is the scaled representation of the FB pin voltage. The scale factor, Iratio, is 3. The FB pin voltage is provided by an external error amplifier, whose output is a function of the power supply output. An FB signal between Vskip and 3 V determines the duty ratio of the controller output. The FB voltage operates in a closed loop with the output voltage to regulate the power supply. It is recommended that an external filter capacitor be placed as close to the FB pin as possible to improve the noise immunity.
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- +
time
PWM Output
180 ns VCS LEB
CS
ID
RCS
VPWM
VCS
NCP1219
Ramp Compensation
Ramp compensation is a known mean to cure subharmonic oscillations. These oscillations take place at half the switching frequency and occur only during continuous conduction mode (CCM) with a duty ratio greater than 50%. To lower the current loop gain, one usually injects 50 to 75% of the inductor current down slope. The NCP1219 generates an internal current ramp that is synchronized with the clock. This current ramp is then routed to the CS pin. Figures 32 and 33 depict how the ramp is generated and utilized. Ramp compensation is simply formed by placing a resistor, Rramp, between the CS pin and the sense resistor.
Ramp current, Iramp Iramp(peak)
Rramp +
(S off,primary
R CS) @ %slope
Iramp(peak) fOSC D
(eq. 5)
where RCS is the current sense resistor and %slope is the percentage of the current downslope to be used for ramp compensation. The NCP1219 has a peak ramp compensation current of 100 mA. A frequency of 65 kHz with an 80% maximum duty ratio corresponds to an 8.1 mA/ms ramp. For a typical flyback design, let's assume that the primary inductance is 350 mH, the converter output is 19 V, the Vf of the output diode is 1 V and the NP:NS ratio is 10:1. The off time primary current slope is given by Equation 6.
(Vout ) V f) LP
NP NS
+ 571 mA ms
(eq. 6)
0
time 80% of period 100% of period
When projected over an RCS of 0.1 W (for example), this becomes 57 mV/ms. If we select 50% of the downslope as the required amount of ramp compensation, then we shall inject 28.5 mV/ms. Therefore, Rramp is simply equal to Equation 7.
Rramp + 28.5 mV ms 8.1 ms
mA
Figure 32. Internal Ramp Compensation Current Source
+ 3.5 kW
(eq. 7)
DRV
Ramp compensation greater than 50% of the inductor down slope can be used if necessary; however, overcompensating will degrade the transient response of the system. The addition of ramp compensation also reduces the total available output power of the system.
Internal Oscillator
Rramp RCS
Clock Current Ramp Oscillator
Iramp(peak) CS
Figure 33. Inserting a Resistor in Series with the Current Sense Information Provides Ramp Compensation
In order to calculate the value of the ramp compensation resistor, Rramp, the off time primary current slope, Soff,primary must be calculated using Equation 4,
(V out ) V f) @ Soff,primary + LP
NP NS (eq. 4)
The internal oscillator of the NCP1219 provides the clock signal that sets the DRV signal high and limits the duty ratio to 80% (typical). The oscillator has a fixed frequency of 65 kHz or 100 kHz. The NCP1219 employs frequency jittering to smooth the EMI signature of the system by spreading the energy of the main switching component across a range of frequencies. An internal low frequency oscillator continuously varies the switching frequency of the controller by 7.5%. The period of modulation is 6 ms, typical. Figure 34 illustrates the oscillator frequency modulation.
where Vout is the converter output voltage, Vf is the forward diode drop of the secondary diode, NP/NS is the primary to secondary turns ratio, and LP is the primary inductance of the transformer. The value of Rramp can be calculated using Equation 5,
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NCP1219
Oscillator Frequency Startup current source is charging the VCC capacitor VCC(on) FOSC + 7.5% FOSC FOSC - 7.5% 6 ms VCC(hiccup) Startup current source turns on when VCC reaches VCC(hiccup) time time Startup current source is off when V CC is VCC(on)
Figure 34. Oscillator Frequency Modulation Gate Drive
The output drive of the NCP1219 is designed to directly drive the gate of an n-channel power MOSFET. The DRV pin is capable of sourcing 500 mA and sinking 800 mA of drive current. It has typical rise and fall times of 30 ns and 20 ns, respectively, driving a 1 nF capacitive load. The power dissipation of the output stage while driving the capacitance of the power MOSFET must be considered when calculating the NCP1219 power dissipation. The driver power dissipation can be calculated using Equation 8,
PDRV + f OSC @ Q G @ V CC
(eq. 8)
The external latch feature allows the circuit designers to implement different kinds of latching protection. Figure 36 shows an example circuit in which a bipolar transistor is used to pull the Skip/latch pin above the latch threshold. The RLIM value is chosen to prevent the Skip/latch pin from exceeding the maximum rated voltage. The NCP1219 applications note (AND8393/D) details several simple circuits to implement overtemperature protection (OTP) and overvoltage protection (OVP). VCC RLIM Fault output Skip/latch HV Cskip Rskip FB CS GND VCC DRV
Figure 35. Latch-off VCC Timing Diagram
where QG is the gate charge of the power MOSFET.
External Latch Input
Board level protection functionality is often incorporated using external circuits to suit a specific application. An external fault condition can be used to disable the controller by bringing the voltage on the Skip/latch pin above the latch threshold, Vlatch (3.9 V typical). When an external fault condition is detected, the DRV signal is stopped, and the controller enters low current operation mode. The external capacitor CCC discharges and VCC drops until VCC(hiccup) is reached. The high voltage startup circuit turns on and Istart charges CCC until VCC(on) is reached. VCC cycles between VCC(on) and VCC(hiccup) until VCC reaches VCC(reset). Voltage must be removed from the HV pin, disabling the startup current and allowing CCC to discharge to VCC(reset). Therefore, the controller is reset by unplugging the power supply from the wall to allow Vbulk to discharge. Figure 35 illustrates the timing diagram of VCC in the latch-off condition.
NCP1219
Figure 36. Circuit Example of an External Latch-off Circuit
An internal blanking filter prevents fast voltage spikes caused by noise from latching the part. However, it is recommended that an external filter capacitor be placed as close as possible to the Skip/latch pin to further improve the noise immunity.
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NCP1219
Skip Cycle Operation
During standby or light load operation the duty ratio on the controller becomes very small. At this point, a significant portion of the power dissipation is related to the power MOSFET switching on and off. To reduce this power dissipation, the NCP1219 "skips" pulses when the FB level drops below the skip threshold. The level at which this occurs is completely adjustable by setting a resistor on the Skip/latch pin. By discontinuing pulses, the output voltage slowly drops and the FB voltage rises. When the FB voltage rises above the Vskip level, DRV is turned back on. This feature produces the timing diagram shown in Figure 37.
Vskip VFB ID Skip
Skip peak current, %ICSSKIP, is the percentage of the maximum peak current at which the controller enters skip mode. %ICSSKIP can be any value from 0 to 43% as defined by Equation 9. However, the higher %ICSSKIP is, the greater the drain current when skip is entered. This increases acoustic noise. Conversely, the lower %ICSSKIP is, the larger the percentage of energy is expended turning the switch on and off. Therefore, it is important to adjust %ICSSKIP to the optimal level for a given application.
%ICSSKIP + V skip 3V @ 100
(eq. 9)
Figure 38 shows the details of the Skip/latch pin circuitry. The voltage on the Skip/latch pin determines the voltage required on the FB pin to place the controller into skip mode. If the pin is left open, the default skip threshold is 1.1 V. This corresponds to a 37% %ICSSKIP (%ICSSKIP = 1.1 V / 3.0 V * 100% = 37%). Therefore, the controller will enter skip mode when the peak current is less than 37% of the maximum peak current.
Figure 37. Skip Operation
2V Skip/latch
+
Rupper 42.0 k R lower 51.3 k
latch-off, reset when V CC < VCC(reset) Vlatch + VSkip Vskip(MAX) Vskip/Latch + -
50 us filter
S RQ
VSkip/latch Rskip
-
Cskip
VFB
Skip Comparator
To DRV latch reset
Figure 38. Skip Adjust Circuit
The skip level is reduced by placing an external resistor, Rskip, between the Skip/latch and GND pins. Figure 39 summarizes the operating voltage regions of the Skip/latch pin.
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NCP1219
Vskip/latch 9.5 V (maximum pin voltage)
Within the adjustable Vskip range, the skip level changes according to Equation 10.
Vskip + 2 V @ (R lower o R skip) (R lower o R skip) ) R upper
(eq. 10)
Controller is latched Vlatch Skip threshold clamped to Vskip(MAX) Vskip(MAX)(maximum skip threshold) Adjustable Vskip range. 0 V (no skip)
An internal clamp limits the skip threshold (Vskip(MAX)) to 1.3 V. Increasing the voltage on the Skip/latch pin beyond the value of the internal clamp will induce no further change in the skip level. This prevents the act of disabling the controller in the presence of an external latch event from causing it to enter skip mode. The relationship between %ICSSKIP, VSkip/latch, Vskip, and Rskip is summarized in Table 4.
Figure 39. NCP1219 VSkip/latch Pin Operating Regions Table 4. %ICSskip and Skip Threshold Relationship with Rskip
%ICSskip 0% 12% 25% 37% 43% 43 % VSkip/latch 0V 0.36 V 0.75 V 1.10 V 2.00 V 3.00 V Vskip 0V 0.36 V 0.75 V 1.10 V 1.30 V 1.30 V Rskip 0W 11.8 kW 52.3 kW Open - - Default Skip Threshold No further increase in Skip threshold No further increase in Skip threshold Never skips - - Comment
External Non-Latched Shutdown
Figure 40 summarizes the operating regions of the FB pin. An external non-latched shutdown can be easily implemented by simply pulling FB below the skip level. This is an inherent feature of the standby skip operation, allowing additional flexibility in the SMPS design.
V FB Fault operation when staying in this region longer than 118 ms 3V PWM operation V skip 0V
opto coupler
Skip/latch HV FB OFF CS GND VCC DRV
NCP1219
Figure 41. Example Circuit for Non-Latched Shutdown Overload Protection
No DRV pulses
Figure 40. NCP1219 Operation Threshold
Figure 41 shows an example implementation of a non-latched shutdown circuit using a bipolar transistor to pull the FB pin low.
Figure 42 details the timer based fault detection circuitry. When an overload (or short circuit) event occurs, the output voltage collapses and the optocoupler does not conduct current. This opens the FB pin and VFB is internally pulled higher than 3.0 V. Since VFB/3 is greater than 1 V, the controller activates an error flag and starts a timer, tOVLD (118 ms typical). If the output recovers during this time, the timer is reset and the device continues to operate normally.
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NCP1219
However, if the fault lasts for more than 118 ms, then the driver turns off and the device enters the VCC double hiccup mode described earlier.
4.8 V
The NCP1219 also has an internal temperature shutdown circuit. If the junction temperature of the controller reaches 155C (typical), the driver turns off and the controller enters double hiccup mode.
Latched and Auto-Retry Options
FB
V FB V FB 3 V SS
+ -
118 ms delay
Fault disable Drv
Soft-start 1 V max
The NCP1219A offers a latched fault circuitry. An overload fault condition detected by the controller results in a latch-off shutdown, requiring the controller to be reset by cycling VCC (removing the ac line input). NCP1219B provides an auto-retry circuit. All fault conditions except the external latch fault result in the controller entering double hiccup mode, attempting to restart the controller every other VCC cycle, as mentioned earlier.
Figure 42. Block Diagram of Timer-Based Fault Detection Table 5. ORDERING INFORMATION
Device NCP1219AD65R2G NCP1219BD65R2G NCP1219AD100R2G Overcurrent Latch Auto-Recovery Latch Frequency 65 kHz 65 kHz 100 kHz Package SOIC-7 (Pb-Free) SOIC-7 (Pb-Free) SOIC-7 (Pb-Free) Shipping 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP1219
PACKAGE DIMENSIONS
SOIC-7 CASE 751U-01 ISSUE D
-A-
8 5
-B- S
1 4
0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
G C -T- H D 7 PL 0.25 (0.010)
M SEATING PLANE
R
X 45 _
J M TB
S
K
A
S
The products described herein (NCP1219) may be covered by one or more of the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221, 6,633,193, 6,587,351, 6,940,320. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP1219/D

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